1. Field of the Invention
This invention relates to an apparatus and a method for driving a liquid crystal display device, capable of removing a screen distortion, implementing a high resolution and implementing a multi channel.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device controls light transmittance of liquid crystal cells in accordance with data signals applied thereto, to thereby display an image. In particular, an active matrix type LCD device includes a switching device for each cell and has various applications, such as a monitor for a computer, an office equipment, and a cellular phone. A thin film transistor (TFT) is generally employed as the switching device for the active matrix type LCD device.
FIG. 1 is a schematic block diagram showing an apparatus for driving a liquid crystal display device according to a related art.
In FIG. 1, a related art LCD driving apparatus includes a liquid crystal display panel 2 having liquid crystal cells Clc arranged in a matrix-like manner at intersections between data lines DL and gate lines GL, a data driver 4 for applying data signals to the data lines DL, a gate driver 6 for applying gate signals to the gate lines GL, and a timing controller 8 for controlling the data driver 4 and the gate driver 6 using synchronizing signals H, V, and DE applied from a system 10.
The liquid crystal display panel 2 includes a plurality of liquid crystal cells Clc arranged, in a matrix-like manner, at the intersections between the data lines DL and the gate lines GL. The thin film transistor TFT provided at each liquid crystal cell Clc applies a data signal from each data line DL to the liquid crystal cell Clc in response to a scanning signal from the gate line GL. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst functions to maintain a voltage of the liquid crystal cell Clc constant.
The data driver 4 converts digital video data R, G and B into analog gamma voltages, i.e., data signals, corresponding to gray level values in response to a data control signal DCS from the timing controller 8, and applies the analog gamma voltages to the data lines DL.
The gate driver 6 sequentially applies a scanning pulse to the gate lines GL in response to a gate control signal GCS from the timing controller 8, thereby selecting horizontal lines of the liquid crystal display panel 2 to be supplied with the data signals.
The system 10 applies vertical/horizontal synchronizing signals V and H, a clock signal DCLK and a data enable signal DE to the timing controller 8. Further, the system 10 compresses a parallel digital data into a serial data using a low voltage differential signal interface (LVDS), and applies the compressed data to the timing controller 8.
The timing controller 8 generates the gate control signal GCS and the data control signal DCS for controlling the gate driver 6 and the data driver 4, respectively, using the vertical/horizontal synchronizing signals V and H, the clock signal DCLK and the data enable signal DE inputted from the system 10. The timing controller 8 also restores the data applied from the system 10 into a parallel data and supplies the restored data to the data driver 4.
A related art system 10 using the LVDS interface sequentially supplies data from the first data integrated circuit (IC) Dr1 to the nth data IC Drn, as shown in FIG. 2. However, since there is a delay in the data supply from the first data IC Dr1 to the nth data IC Drn, it is difficult to provide a high speed driving of a liquid crystal display device having a high resolution.